1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a circuit and a method for transforming a data input/output format in a parallel bit test (PBT).
2. Description of the Related Art
A parallel bit test (PBT) is used to check failures of memory cells and write/read paths by writing and reading data to and from the memory cells of a semiconductor memory device in parallel. If the number of data input/output pins (DQ) is reduced in the parallel bit test (PBT), more memory devices can be tested at the same time. For example, if 16 monitoring pins can be used in test equipment, two X8 mode memory devices, four X4 mode memory devices, or eight X2 mode memory devices can be tested in the test equipment.
Therefore, it is advantageous in terms of time and costs to test memory devices using the PBT with a decreased number of data input/output pins DQ. In general, a circuit for transforming a data input/output format is used to reduce the number of data input/output pins (DQ) in the PBT.
FIG. 1 is a view of a X4 data input/output format, and FIG. 2 is a view of a conventional circuit for transforming a data input/output format from a X4 mode to a X2 mode. If the number, of memory cells (MC), e.a., MC1, MC2. MC4, MC5, connected to a column select line CSL is equal to the number of data input pins DIN0-DIN3, no problems occur. That is, all types of data patterns can be tested by writing and reading the data patterns to and from four memory cells MC1, MC2, MC4, MC5, while using four data input pins DIN0-DIN3.
However, in the circuit of FIG. 2, two memory cells are connected to one data input pin through a circuit 20 for transforming a data input/output format. That is, two memory cells MC0 and MC1 are connected to a data input pin DIN0, and two memory cells MC4 and MC5 are connected to a data input pin DIN1. As a result, the number of memory cells MC0, MC1, MC4, MC5 connected to one column selection line CSL is greater than the number of data input pins DIN0 and DIN1.
In this case, the types of data patterns that can be written to the memory cells MC0-MC5 are limited. The following Table 1 shows types of data patterns that can be written to the memory cells MC1, MC2, MC4, MC5 in the circuit of FIG. 2.
TABLE 1Memory cellData patternMC00011MC10011MC40101MC50101
However, when data patterns of Table 1 are used, it is impossible to check failures between two adjacent input/output lines, e.g., between an input/output line connected to the memory cell MC0 and an input/output line connected to the memory cell MC1 or between an input/output line connected to the memory cell MC4 and an input/output line connected to the memory cell MC5.
This is because it is impossible to generate a data pattern, which can be written with different data in the memory cells MC0 and MC1 or MC4 and MC5, i.e., (0,1,0,1) or (1,0,1,0), by the conventional circuit 20 for transforming an input/output format shown in FIG. 2.